The PCI EXPRESS system is the next generation of PCI (Peripheral Component Interconnect), which is a standard interconnection system that enables the transfer of data between a host device 112 and an attached application layer device 114 of a data transfer system 100, FIG. 1. The PCI EXPRESS system protocol is implemented using PCI EXPRESS system core 116. PCI EXPRESS system core 116 is a hardware controller used to identify and resolve the PCI EXPRESS system protocol layers: the physical/mac layer 118, the link layer 120 and the transaction layer 122. The data is delivered through an application layer interface 124 to the attached application layer device 114.
The PCI EXPRESS system protocol is a very fast, bandwidth rich protocol, enabling a variety of applications to be implemented through a PCI EXPRESS system link. Application layer devices 114 can include bandwidth-consuming applications, such as file transfers and multimedia files, latency-sensitive applications, such as real-time video and voice streaming applications, and applications requiring both high bandwidth and low latency, such as video conferencing.
The application layer interface 124 connects the PCI EXPRESS system core 116 to the application layer device 114. The application layer device 114 may be a single, common address/data bus having control signals to insure errorless handshakes between the host 114 and any type of application. For example, the application layer device may be a switch or router connected between the PCI EXPRESS system core 116 and a number of clients that communicate with the host 112. The application layer device in such a case routes incoming packets to the appropriate client (not shown).
The application layer interface 124 is driven by the transaction layer architecture 122 of the PCI EXPRESS system core 116. The transaction layer architecture 122 of the PCI EXPRESS system core 116 typically consists of six FIFO buffers: a non-posted header buffer “NP H” 126, a non-posted data buffer “NP D” 128, a posted header buffer “P H” 130, a posted data buffer “P D” 132, a completion header buffer “C H” 134 and a completion data buffer “C D” 136. The six buffers 126-136 are needed to implement the PCI EXPRESS system reordering rules for three different types of transfers: 1) posted transfers (typically memory write transfers); 2) non-posted transfers (typically memory read transfers); and 3) completion transfers (also called “read response” transfers). The PCI EXPRESS system reordering rules are set by the PCI EXPRESS system Standard and described in the PCI EXPRESS system Base Specification.
One of the PCI EXPRESS system specific mechanisms is TRANSACTION_ID-based routing, which is handled in PCI EXPRESS system Core. The TRANSACTION_ID is a 24-bit wide field embedded into the PCI Express data packet. Its main functionality is to provide a unique identifier for the sender of a data packet. If a data packet transaction sent by a requesting device requires an acknowledgment-type return packet, or completion, the TRANSACTION_ID field of the data packet transaction provides information to route the returning packet to the original requesting device. The TRANSACTION_ID includes a Requester ID field, which includes all necessary information to identify the high-level requesting device, such as a chip within the system, that initiated the data packet and an 8-bit TAG field. The TAG field is provided in order to uniquely identify the specific client within the specific high-level requesting device from which the data packet transaction was issued. For example, the same requesting device can issue more than one transaction within a particular period of time. All issued transactions might require a completion from the receiver. All Requestor IDs for completions received by the same requesting device would look the same except for the unique TAG field. The TAG field is a tool provided by the PCI EXPRESS system protocol in order to distinguish different completion packets coming to the same requesting device with the same bus number and the same function number.
The structure of the TAG field is typically used as a read request counter. A read request counter is basically an 8-bit counter that gets updated each time a read request transfer is sent by a device. For example, the first transfer from a particular device will have the TAG field set to 0, the second transfer will have the field set to 1 and so forth. Once a completion (read response) packet is received by the requesting device, the particular unique TAG will be released for reuse.
Based on this usage of the TAG field, the maximum outstanding number of transactions per device is 28=256 read request transactions. Such a number of outstanding transactions is typically seen as too large, as it might “clog” the system with outstanding unfinished transactions. The PCI EXPRESS system protocol provides the way to limit the TAG field to only 5 bits. In that case the upper most 3 bits are set to 0. Regardless, if the TAG field is used as 5-bit field or 8-bit field by the requesting device, the completing device is required to return the entire TAG field (along with the rest of the TRANSACTION_ID) without any modifications.
Upon receiving the returned TRANSACTION_ID in the form of a completion, the application must read the TAG field and resort to a look-up table in order to determine which client within the requesting device send the read request, based on the number set in the TAG field of the Transaction ID. The reference to the look-up table takes time, which increases the latency of the data transfer system. This method requires a large memory table, which slows down the process, as valuable time is lost on reading the tables. Certain chip technologies might also reject running the chips with desirable frequencies, as the routing tables tend to consume large portions of ASIC routing channels.